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The Cell Processor - A Technology Update
The Cell Processor is billed as tomorrow's "supercomputer on a chip".
Development of the cell processor is a result of a partnership between
Sony, Toshiba & IBM way back in 2001. Sony has earmarked nearly
US $ 4.5 billion (for the 3 year period ending March 31, 2007) to
develop semiconductors for Cell Processors & related devices. And
that it plans to start test production of these chips as early as
2005 Q1.
Sony plans to launch powerful broadband TV sets in 2006 which will
combine the functions of television, gaming box and PC. These TV
sets of the future will use the soon-to-be-released cell processor
technology. Right on target for the final leg of convergence of
Internet, entertainment & communications?
The Next Generation Processor
Just as cells in our body unite to form combined physical systems
with complex capabilities, a "cell" processor architecture will
allow all kinds of electronic devices (from consumer products to
supercomputers) to work together as combination devices.
The Cell Processor was first announced in 2001 by the Sony, Toshiba
& IBM combine. The purpose of the partnership was to design an architecture
for a system-on-a-chip (SoC) design. Code-named Cell, chips based
on the architecture will be able to use ultra high-speed broadband
connectivity to inter-operate with one another as a combined unit,
quite like the way neural cells inter-operate over the brain's network.
Expected to go into trial production within the next 6 months, a
single cell will produce 100 times more processing power than conventional
processors. (Comparision with the current Intel PIV 2.4 GHz). Moreover,
it will simultaneously be able to send large chunks of information
through high-speed networks.
Inside the Cell Processor
Each cell processor may comprise of a pool of processor cores, typically
16. (These processor cores need not be identical).
The on-chip scheduling software is responsible for allocating resources
from this pool to demands on a task-to-task basis. For instance,
Task #1 may be a 3D drawing engine, requesting cycles from the same
pool for rendering an image.
Simultaneously, a set of software routines may request cycles from
the same pool for processing audio signals. And a third demand may
concurrently come from a gaming software. And so on. Depending on
a combination of availability and a need to complete specific tasks,
processors are grouped together dynamically into "task forces".
And each temporary combination of processors will constantly try
to adjust to the load by acquiring (or releasing) new processors
from (to) the pool.
Intel's EPIC and Sun's MAJC Initiatives
Meanwhile, current chip majors Intel (in partnership with HP) and
Sun have also been working on their own versions of high-performance
multi-processor system-on-chip (SoC) architecture.
Intel has been working (with HP since June 1997) on the EPIC (Explicitly
Parallel Instruction Computing), while Sun has been developing their
MAJC ( Major Architecture for Java Computing).
The major difference in these technologies seems to be a certain
amount of dependency on the hardware "instruction set" as compared
to the cell processor. (This seems natural when you consider that
both partnerships have a single major computer manufacturer. The
cell processor combine on the other hand, has 2 manufacturers -
IBM & Toshiba - who are seen to have accepted the development as
a completely revolutionary new design with little backward compatibility
issues.)
Media Rich Computing
For the past 3 decades, starting with the Apple, personal computing
has been steadily progressing towards "media richness". On another
level, entertainment has become a part of everything. (Another way
to look at it is that everything has to be entertaining.) From a
computing angle, the more media rich computing becomes, the more
the processing. (Typically for parallel processing techniques like
multi-threading, vector processing, and super scalar execution.)
And the more complex the implementation, the more the need for easy
scalability.
It makes sense to build new generation chips with scalability &
parallel processing architecture, instead of retro-fitting chips
(which were originally designed for the desktop PC or server) in
an embedded or console environment.
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